Hardware Description Languages (HDL)

Hardware description languages are used to compute the hardware structure of a circuit that efficiently produces the desired Boolean function output during digital circuit design. In other words, they are employed by logic synthesis tools to generate a netlist that specifies the components within the circuit and their interconnections. This generated netlist is then used for transistor-level circuit simulation and verification. Based on the results of these processes, design iterations are performed when necessary to correct identified errors.

Previously, circuit designers manually solved Boolean equations to express a specific function using a series of logic gates. However, the intensive manual calculations and the potential for human error made this process inefficient. Additionally, because these calculations depended on the underlying semiconductor-level electronic technology, they had to be repeated for circuits using different technologies. For these reasons, designers were led to develop systems capable of operating at a higher level of abstraction. Although the first examples of hardware description languages appeared in the 1950s, widespread adoption began toward the end of the 1980s with the development and standardization of Verilog and VHDL (VSIC HDL).

VERILOG

The name Verilog is derived from the combination of the English words “Verification” and “Logic.” Syntactically, Verilog resembles the C language and has a simpler structure compared to VHDL. Originally designed in 1984 by Gateway Design Automation for internal company use only, Verilog became publicly available as a standard in 1990 after the company was acquired by Cadence. It was later adopted as an IEEE standard in 1995.

In Verilog, there are two main categories of data types: “net” and “variable.” Net data types represent the wires connecting circuit components. They do not hold values by themselves and therefore require a driver to assign a value. When the driver’s value changes, the net’s value changes accordingly. Variable data types, on the other hand, retain their assigned value until a new assignment is made. These types behave like variables in traditional software languages, supporting sequential assignments without concurrency.

The set of values a signal can take in Verilog is shown in Table 1 below.

^{Value Set Used in Verilog}

In Verilog, the ‘Blocking’ and ‘Non-Blocking’ constructs are used to control whether assignments are executed sequentially or concurrently. The ‘Blocking’ construct specifies that assignments are performed independently and in sequence. The ‘Non-Blocking’ construct indicates that assignments occur simultaneously, with no time delay between them. The resulting circuits generated by these two constructs can be significantly different.

An example code snippet using the ‘Non-Blocking’ construct is shown below. The circuit schematic generated by this code is illustrated in Figure 1.

Circuit Schematic Generated by Non-Blocking Construct (Figure created by the author.)

An equivalent code snippet using the ‘Blocking’ construct is provided below. The circuit schematic generated by this code is shown in Figure 2.

Circuit Schematic Generated by Blocking Construct (Figure created by the author.)

VHDL

VHDL is a combination of the terms “Very High Speed Integrated Circuit” (VSIC) and “Hardware Description Language” (HDL). It features a detailed syntax similar to the Ada programming language. VHDL was first developed in 1981 by the United States Department of Defense. Following its standardization by IEEE in 1987, the language has undergone numerous updates and revisions up to the present day.

Two commonly used data types in VHDL are “bit” and “std_logic.” The bit data type can only take the values ‘0’ and ‘1,’ whereas std_logic can represent a wider range of values. The possible values for std_logic are listed in Table 2 below.

^{Value Set Used in VHDL}